This invention relates generally to a system and method for updating the data stored in a cache memory and in particular to a system and method for updating the data stored in a cache memory attached to an input/output system.
Computer systems often have one or more add-on and/or input/output systems attached to the computer system that perform some dedicated input/output function. These add-on and/or input/output systems sometimes include a processor which executes instructions to process the input and/or output data. For example, a digital signal processor may process incoming data and send the processed data on to the main or host CPU. The processor in the input/output system may also need to access data contained in the main memory of the computer system to which it is attached. To decrease the time required to access data contained in the main memory of the computer system and increase the execution speed of the processor in the input/output system, a cache memory system connected between the main memory and the input/output processor may be provided. The cache memory system may include a plurality of sections of memory, called memory pages, which have a predetermined size and may be rapidly accessed by the processor because the cache memory system has a faster access time than the main memory of the computer system. Each memory page of the cache memory may contain a copy of a selected portion of the main memory of the computer system. Each memory page in the cache memory may further include a plurality of cache lines. The cache memory is typically smaller than the main memory of the computer system and cannot store all the data contained in the main memory at all times. Therefore, it is desirable to determine automatically which memory pages of the cache memory have data that is most often requested by the input/output processor. The most often requested memory pages are then maintained in the cache memory because data already in the cache memory may be accessed more rapidly by the input/output processor.
When the processor, in the add-on or input/output system, attempts to access data in the main memory, a controller of the cache memory determines if the cache memory currently contains the requested data. If it does not currently contain the requested data, a memory page within the cache memory is selected to hold a cache memory page sized portion in the main memory which includes the requested data. The data requested from the main memory and any data in the cache line with the requested data is then transferred into the cache memory so that is may be provided to the processor and stored for subsequent accesses by the processor in the add-on or input/output system (hereinafter referred to as the processor).
Each cache line may store two bits of data which indicate the state of the data in the cache line. When data is read into a cache line, a valid bit is set indicating that the data in the cache line was loaded from the main memory and may be used by the processor. Any subsequent accesses to that cache line will return the requested data without having to retrieve the data from the main memory. When the processor modifies the data in a cache line, a modified bit is set indicating that the data in the cache line is different than the main memory and must be written back into the main memory to maintain the coherency of the cache memory and the main memory. In a typical cache memory system used with a multi-processor computer system, for example, coherency between the main memory and the cache memory must be maintained. This is because the main memory is shared by multiple processors and modifications to a cache line should be quickly represented in the main memory. In doing this, the time required to process page misses is reduced but this is achieved by maintaining a high amount of traffic on the bus connecting the cache memory with the main memory of the computer system.
An input/output system, however, may request data from a particular input/output portion of the main memory and the input/output portion of the main memory may only be accessed by the input/output system so that it is not necessary to write back modified cache lines immediately to the main memory. Therefore, a write-back cache memory may be used with these input/output systems. In a write-back cache memory, data modified by the input/output processor is first stored in a cache line in the cache memory and then subsequently written back into the main memory when either the cache memory has time to write the data back or the page containing the modified cache line is needed to store new data requested by the input/output processor.
Because the cache memory is smaller in size than the main memory, all of the data in the main memory cannot be stored in the cache memory. Therefore, it is desirable to provide a system and method for updating the data in the cache memory attached to an input/output system. Typical cache memories write modified cache lines back to the main memory immediately due to the coherency problem described above which reduces the speed of the cache memory. However, an input/output system that uses a predetermined portion of the main memory does not have this coherency problem and thus, it is also desirable to provide a write-back cache memory that efficiently updates the data in the cache memory in a predetermined manner. Thus, there is a need for a system and method for updating the data stored in a cache memory attached to an input/output system which avoid these and other problems of known systems and methods, and it is to this end that the present invention is directed.